The development of high-capacity PCBs:
The development of high-capacity PCBs and packaging substrates using different and additional production processes was the theme of the 13th Technical Snapshot webinar presented by the EIPC on November 24. Launched and moderated by technical director Tarja Rapala-Virtanen.
In Switzerland, Daniel Schulze, application engineering manager at Disconex, made the opening remarks, "Solid RF packing and miniaturization substrates." He explained that with their long-established capabilities on high-performance PCBs in flex, rigid-flex and rigid multilayer technologies, it made sense for Dyconex to use its technology in developing professional IC substrates.
He illustrated the diversity of partial packaging and how it evolved from the plastic ball grid series of the 1990s to integrated 3D circuits, fan-out-chip-on-substrate packages and modern silicon photonics devices.
"Something has to be reduced and this is usually PCB," he said as he discussed the cause of high density and the factors that lead the industry to smaller devices while avoiding any compromise of reliability or performance.
It reviewed the current requirements for packing substrates, usually consisting of large chips with additional connectivity and high-frequency performance, and introduced a long list of desirable physical, mechanical, thermal and electrical properties, as well as a slight reduction of circuit characteristics.
Dynex has designed a composite PCB packaging, which combines pattern elements to be solved, blind vias with any layout, cord binding, flip-chip pitch, adhesives, RF features, and link stress testing. This was used to produce and evaluate a range of glass-reinforced and non-reinforced materials.
Output processing acquired lines and spaces up to 18 microns; semi-additive processing can benefit up to 10 microns. For laser-drilled any-layer vias stacked blind, 50-micron vias in 150-micron pads have become the norm, and the standard ones were 40-micron vias in 90-micron pads. Schulze explained how to interconnect stress tests have been used to demonstrate the reliability of 10-layer coated BT-epoxy with a design of 30 micron dielectric layers and 50-micron vias in 120 pads. -micron.
Demonstrated examples of substrates for specific applications: high-performance HDI interposer with a depth of more than 30 mm using a very dense 150-micron pitch ASIC substrate, a package-on-package module with frame and mould filling. And a packaged super-miniaturization package based on flexible polyimide. Dynex can provide engineering support and rapid modelling service for packaging substrates to building materials and designs similar to high-end Asian products, and create fast, flexible products that range from slow to medium volume.
Living with the topic of the smallest substrates, Lars Böttcher, head of embedding and substrates and Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration in Berlin, discussed the development of externally and panel-based packaging technology.
He began with an introduction to the redistribution process, those copper connectors that connect electrically one part of the semiconductor package to the other and reviewed additional procedures as a means of lowering the line tone. Modified semi-additive processing, mSAP, based on 1.3 to 3 microns of clad foil and 1 to 2 microns of gas-free, used for lines and space over 1 micron 20. Semi-additive processing, SAP, based on 1 to 2 microns of electroless copper, can achieve lines and plays in a range of 10-20 microns.
Advanced semi-additive processing, aSAP based on 50 to 500 nanometers of copper-plated vapour, can reach lines and spaces in the range of 10-5 microns. Böttcher described the process flow: The standard substrate was based on a non-solid, saturated or unfilled dielectric, provided in different ways; the dry film is the simplest. This may be photographic or laser pierced to form vias, then covered with layers of titanium and copper seeds by evaporation. The dry film's high-resolution liquid or photoresist was applied and adjusted for direct film or adaptive imaging, followed by semi-additive copper plating, photoresist removal, and distinct separation.
Demonstrated the sequence of a process for constructing a redistribution layer consisting of 5-micron coated copper tracks and spaces to apply for embedding.
With direct communication, the basic options are laser or photo vias, and Böttcher reviewed the benefits and limitations. Photo vias can provide high accuracy and adjustment of registration, and the process is faster, but there are process limitations in the use and development of dielectric filters. Demonstrated microsection examples of vias formed by both methods. The third option, recently introduced, was plasma vias, although there were still some problems with plasma embedding speed, hole formation and similarity to be considered.
Böttcher explored the concept of dying embedding in panel-level installation, using PCB laminate core to limit downtime shifts and provide improved management stability. He showed the sequence of the process in which the death of the copper pillars is inserted into the holes previously constructed in the context of the PCB, which is secured with adhesive tape. Vacuum lamination with dielectric film successfully embedded dies from one side. The sticky film is removed to expose the copper pillars, and these are embedded with a second vacuum lamination. Vias are then composed of laser, image or plasma, and redistribution layers created by SAP copper filter before separating packages.
He showed real examples at each stage of the process and emphasized that flexible thinking is the key to overcoming the challenges of alignment and enrollment.
In his introductory remarks, Rapala-Virtanen noted that the principles of additional production would gradually be adopted in the industry over the coming years, and new production methods would be developed. Introducing Michael Schleicher, a printed circuit design expert with Semikron Electronics Nuremberg and a member of the board of directors of FED, the German PCB designers' council, outlined the disruptive approach to the construction and development of additional circuit board tools.
After reviewing the bare die attach and die connection technology modules developed at Semikron, he focused on silver printing. He explained how inkjet techniques were developed and adapted to install functional silver ink into complex patterns. Market forecasts show significant growth in inkjet technology in add-on electronics. Schleicher demonstrated examples of rapidly changing prototype multilayer circuits with 70-micron lines and 100-micron spaces, produced on a three-dimensional interactive printer using inductive and dielectric products based on nanotechnology.
Additional production allowed for integrating many third-party components into the traditional circuit configuration of the same durability. It opened up a more comprehensive range of design options, providing a disruptive approach to future building solutions.
Schleicher's design feature drawings include opportunities such as forming a three-dimensional substrate, the path of any layer, the angle line, any angle, angles, angles, not a vertical line, a straight outflow, a real twisted line. And lots of harness design and defence options.
Existing concepts of process flow, eCAD tools, and data formats will need to change to get the benefits of such technology. The FED Working Group on Three Electronic Technology, Arbeitskreis 3D-Electronics, founded in 2016, learns the feasibility and collects information on data formats, design tools, and technical terms.
A series of PCB tool Schleicher schemes of additionally produced substrates demonstrated the flow of design from a piece of two-dimensional library information using two-dimensional eCAD, followed by a three-dimensional translation using mCAD tools, followed by three-dimensional data production.
The working group proposed a phase-based electronic matrix based on location or position, primary material, active fluid and production data. Complexity is calculated as a series of levels from one to five. Level 1 refers to a circuit with a flat surface made of one material. Level 5 represents a fully three-dimensional printed device that combines embedded and selective components and space.
Rapala-Virtanen masterfully conducted the busy question-and-answer session before closing the webinar, announcing that the Technical Snapshots will continue in 2022. He also enjoyed telling the first live EIPC event since its closure — a conference in Frankfurt on February 10 — certainly something to look forward to.